Contatto di riferimento: Laura Basiricò
Partecipanti: Diego Marini Dipartimento di Fisica e Astronomia, Università di Bologna Consiglio Nazionale delle Ricerche di Bologna, Istituto per la Microelettronica e i Microsistemi
Silicon photonics leverages the optical, electrical and material properties of silicon and the mature complementary metal-oxide semiconductor (CMOS) nanofabrication technique to develop on-chip photonic integration.
Silicon photonics is holding the promise for overcoming the limits of the actually employed electronic interconnections in terms of bandwidth, wiring density and power consumption by realizing optical functionalities on high refractive index contrast silicon-oninsulator (SOI) platform. The effects proposed in literature for the wavelength resonance tuning of the switching devices, i.e. the thermo-optical (TO) effect and free-carrier dispersion (FCD) induced electro-optic (EO) effect, exhibit non-negligible power consumption and are characterized by slow response time (TO) or high optical propagation loss (FCD-EO).
The MINOS project aims at exploring the recently discovered stress-induced Pockels effect in strained silicon, i.e. the variation of the refractive index as a linear function of an applied electric field, for realizing fast and CMOS compatible microring resonator based switching devices. In this work we report a study on the lattice deformation induced by a silicon nitride (Si3N4) film deposited onto silicon photonics structures (450 nm x 220 nm). In particular, simulations of stress and strain distributions on single and coupled ribs structures across the nitride-to-silicon interface were performed along with an estimation of the optical properties of strained SOI optical waveguides.
Finally, Convergent Beam Electron Diffraction (CBED) technique was carried out to perform locally accurate strain measurements on the microfabricated structures. Furthermore an analysis of the coupling structures employable in the optical characterization of the future manufactured devices as interface between the chip under test and measuring instrument is reported.